1. Field of the Invention
This invention relates to a semiconductor memory device, in which two data areas, i.e., a high-speed accessing area and a large capacity storing area, are set.
2. Description of the Related Art
There is increased a demand for NAND-type flash memories in accordance with increasing of the demand for mobile devices, which deal with large capacitive data such as a still or moving image. In the recent flash memories, since it is used such a multi level data storage scheme that two or more bits are stored in one memory cell, it has become possible to store a quantity of information with a relatively small chip area.
NAND-type flash memories are not suitable for a high speed random access use because the cell current is small, i.e., about one dozens in comparison with that of NOR-type flash memories. Therefore, in the conventional NAND-type flash memory, the data transmitting rate is substantially increased in such a way that data are read in a data buffer and then serially output, whereby it is made adaptable to a high speed system via a DRAM.
In the conventional NAND-type flash memories, cell information read is performed with a latch-type sense amplifier, in which the latch is selectively inverted in accordance with whether the charge in the latch is discharged or not based on the cell's ON/OFF. With this sense scheme, it takes some micro seconds to access a memory cell and read data thereof.
Further, in the multi-level data storage scheme, it is difficult to set a word line voltage at a read time to be sufficiently higher in comparison with the cell threshold voltage, and the cell current is not more than about several hundreds nA. To improve the read performance of the NAND-type flash memory, it is in need of sensing a small cell current at a high rate.
As a sense amplifier sensing a small cell current at a high rate, there has already been provided such a latch-type and current-sensing type of sense amplifier that amplifies a cell current difference between a memory cell and a reference cell (for example, refer to JP-A-2005-285161).
In the currently used mobile devices, it is used such a configuration that program data such as OS and the like are stored in a NOR-type flash memory capable of high-speed accessing while a large capacitive file data such as image data, music data and the like are stored in a NAND-type flash memory. That is, since it is not required of the program data to be often rewritten, a NOR-type flash memory with a low write speed is used as a ROM. While, since the NOR-type flash memory is random accessible at a high rate, it is directly coupled to a CPU, and serves for directly code-executing.
Therefore, in case a code data is stored in the NAND-type flash memory, it is copied to a buffer memory such as DRAM, and then the code is executed from the DRAM. Further, the NAND-type flash memory control unit not only performs data input/output transferring but also serves as an address transformation function that converts a logic address input from the external to a physical address, and an ECC function that detects and corrects errors in the read out data.
However, in case the above-described two-chip configuration with a NOR-type flash memory and a NAND-type flash memory is used, both of the system cost and the package area increase. Therefore, it will be desired to use one chip while it is random-accessible and storable with a large quantity of data.
In the conventional. NAND-type flash memory, a sector containing certain bits serves as an access unit, and sequential access will be performed. Therefore, the NAND-type flash memory is not adaptable to random access necessary for a CPU when executing a program such as OS. Therefore, in case a NAND-type flash memory is used in place of a NOR-type flash memory, to execute the program such as OS stored in the NAND-type flash memory, it is in need of outputting the program to a DRAM.
To achieve the above-described system, it is required to prepare a small boot-use ROM such as a mask ROM, a NOR-type flash memory and the like, and store such software that executes previous processing for transferring the program stored in the NAND-type flash memory to a DRAM and for executing it (for example, refer to JP-A-2005-10942).
Since, a cost of a boot-use ROM becomes usually lower as capacity thereof becomes smaller, the software stored in the ROM is limited in magnitude to a minimum as necessary. In a conventional case, stored in the boot-use ROM are only an instruction code used for initially setting an external bus control unit and a memory control unit and another instruction code used for transferring the program stored in the NAND-type flash memory to a DRAM.